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W9816G6CB 512k 2 banks 16 bits sdram table of contents- 1. general des cription ......................................................................................................... 3 2. features ....................................................................................................................... .......... 3 3. available par t number ..................................................................................................... 3 4. ball config uration ............................................................................................................ 4 5. pin descri ption ................................................................................................................ ..... 5 6. block di agram .................................................................................................................. .... 6 7. functional des cription ................................................................................................... 7 7.1 power up and init ialization ............................................................................................. 7 7.2 programming mode register .......................................................................................... 7 7.3 bank ac tivate command ................................................................................................ 7 7.4 read and write a ccess m odes ...................................................................................... 7 7.5 burst read command .................................................................................................... 8 7.6 burs t write command .................................................................................................... 8 7.7 read interrupted by a read ........................................................................................... 8 7.8 read interrupted b y a w r i t e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.9 write interrupted by a write ............................................................................................ 8 7.10 write interrupted b y a r e a d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.11 burs t stop command ..................................................................................................... 8 7.12 addressing sequence of sequential mode .................................................................... 9 7.13 addressing sequence of interleave mode ..................................................................... 9 7.14 auto-prec har ge comm and ........................................................................................... 10 7.15 prec harge co mmand .................................................................................................... 10 7.16 self refres h comm and ................................................................................................ 10 7.17 power down mode ....................................................................................................... 11 7.18 no operati on comm and ............................................................................................... 11 7.19 des e lec t command ...................................................................................................... 11 7.20 clock sus pend mode .................................................................................................... 11 8. operatio n mo de ................................................................................................................. 12 9. electrical chara cteristi cs ......................................................................................... 13 9.1 abs o lute maxi mum rati ngs .......................................................................................... 13 9.2 recommended dc operat ing condi tions .................................................................... 13 publ i c at i on rel e ase dat e : aug. 23, 2007 - 1 - revi si on a3
W9816G6CB 9.3 capacitanc e .................................................................................................................. 13 9.4 dc charac teri s t ic s ........................................................................................................ 14 9.5 ac charac te ris t ic s ........................................................................................................ 15 10. timing w aveforms ............................................................................................................. 17 10.1 command input timing ................................................................................................ 17 10.2 read timi n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.3 control timing of i nput/output data ............................................................................. 19 10.4 mode register set cycle .............................................................................................. 20 11. operating timi ng example ............................................................................................. 21 11.1 interleaved bank read (burst length = 4, cas latency = 3) ...................................... 21 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-prec harge) ........... 22 11.3 interleaved bank read (burst length = 8, cas latency = 3) ...................................... 23 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-prec harge) ........... 24 11.5 interleaved bank write (burst lengt h = 8) ................................................................... 25 11.6 interleaved bank write (burst length = 8, auto -prechar ge) ........................................ 26 11.7 page mode read (burst length = 4, cas lat ency = 3) .............................................. 27 11.8 page mode read / write (burst length = 8, cas latency = 3) ................................... 28 11.9 auto precharge read (burst lengt h = 4, cas lat ency = 3) ........................................ 29 11.10 auto precharge write (burst lengt h = 4) .................................................................... 30 11.11 auto refres h cyc l e ..................................................................................................... 31 11.12 self refres h cyc l e ....................................................................................................... 32 11.13 burst read and single write (burst length = 4, cas latency = 3) ........................... 33 11.14 power down mode ...................................................................................................... 34 11.15 auto-precharge timi ng (read cy cle) ......................................................................... 35 11.16 auto-precharge timi ng (write cy cle) .......................................................................... 36 11.17 timing chart of read to write cycle ........................................................................... 37 11.18 timing chart of write to read cycle ........................................................................... 37 11.19 timing chart of burst stop cy cle (burst st op comm and) .......................................... 38 11.20 timing chart of burst stop cycle (prechar ge comm and) .......................................... 38 11.21 cke/dqm input timi ng (write cy cle) ......................................................................... 39 11.22 cke/dqm input timi ng (read cy cle) ......................................................................... 40 12. package specific ation .................................................................................................... 41 12.1 vfbga60ball (6.4x10.10 mm,ball pitc h:0.65mm, ?= 0.4mm) ..................................... 41 13. revision history ............................................................................................................... .4 2 publ i c at i on rel e ase dat e : aug. 23, 2007 - 2 - revi si on a3
W9816G6CB 1. general description W9816G6CB is a high-speed synchronous dynamic random access memory (sdram), organized as 512k words 2 banks 16 bits. using pipelined architecture and 0.13 m process technology, accesses to the sdram are bur st oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically generat ed by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving among internal banks to hide the precharging time. by having a programmable mode register, the sy stem can change burst l ength, latency cycle, interleave or sequential burst to maximize its perfo rmance. W9816G6CB is ideal for main memory in high performance applications. 2. features ? 2.7v~3.6v power supply for -7 speed grade ? 3.3v 0.3v power supply for -6 speed grade ? 524,288 words x 2 banks x 16 bits organization ? self refresh current: standard and low power ? cas latency: 2 and 3 ? burst length: 1, 2, 4, 8, and full page ? burst read, single write mode ? byte data controlled by udqm and ldqm ? auto-precharge and controlled precharge ? 4k refresh cycles/64 ms ? interface: lvttl ? package: vfbga 60 balls pitch=0.65mm, using pb free with rohs compliant 3. available part number part number speed (cl = 3) sel f ref r esh current (max.) w 9 8 1 6 g 6 c b - 6 1 6 6 m h z 2 m a w 9 8 1 6 g 6 c b - 7 1 4 3 m h z 2 m a publ i c at i on rel e ase dat e : aug. 23, 2007 - 3 - revi si on a3
W9816G6CB 4. ball configuration bottom view 76 21 c b a p n g d e m h l f k r j vss vss dq14 dq13 dq12 dq10 dq8 nc nc nc cke ba a8 a6 dq9 dq15 a4 vssq vddq dq11 vssq nc nc udqm clk nc a9 a7 a5 vddq vdd vdd dq1 dq2 dq3 dq5 dq7 nc we# cas# cs# nc a10 a1 dq6 dq0 a3 vddq vssq dq4 vddq nc nc ldqm ras# nc nc a0 a2 vssq top view 7 6 2 1 c b a p n g d e m h l f k r j vss vss dq14 dq13 dq12 dq10 dq8 nc nc nc cke ba a8 a6 dq9 dq15 a4 vssq vddq dq11 vssq nc nc udqm clk nc a9 a7 a5 vddq vdd vdd dq1 dq2 dq3 dq5 dq7 nc we# cas# cs# nc a10 a1 dq6 dq0 a3 vddq vssq dq4 vddq nc nc ldqm ras# nc nc a0 a2 vssq publ i c at i on rel e ase dat e : aug. 23, 2007 - 4 - revi si on a3
W9816G6CB 5. pin description ball- location ball name f u n c t i o n d e s c r i p t i o n n6, p7, p6, r6, r2, p2, p1, n2, n1, m2, n7 a0 ? a10 address multiplexed pins for row and column address. row address: a0 ? a10. column address: a0 ? a7. m 1 b a b a n k a d d r e s s select bank to activate during row address latch time, or bank to read/write during column address latc h time. a6, b7, c7, d7, d6, e7, f7, g7, g1, f1, e1, d2, d1, c1, b1, a2, dq0 ? dq15 data input/ output multiplexed pins for data input and output. l7 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. k6 ras row address strobe command input. when sampled at the rising edge o f t he clock, ras , cas and we define the operation to be executed. k7 cas column address strobe referred to ras j7 we write enable referred to ras j2/ j 6 udqm/ ldqm input/output mask the output buffer is placed at hi-z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. k 2 c l k c l o c k i n p u t s system clock used to sample inputs on the rising edge of clock. l 1 c k e c l o c k e n a b l e cke controls the clock activation and deactivation. w hen cke is low, power down mode, suspend mode, or self refresh mode is entered. a7, r7 v cc p o w e r ( + 3 . 3 v ) power for input buffers and logic circuit inside dram. a1, r1 v ss g r o u n d ground for input buffers and logic circuit inside dram. b6, c2, e6, f2 v ccq power (+3.3v) for i/o buffer separated power from v cc , used for output buffers to improve noise immunity. b2, c6, e2, f6 v ss q ground for i/o buffer separated ground from v ss , used for output buffers to improve noise immunity. g2, g6, h1, h2, h6, h7, j 1 , k1, l2, l6, m6, m7 n c n o connection no connection. (nc pin should be connected to gnd or floating) publ i c at i on rel e ase dat e : aug. 23, 2007 - 5 - revi si on a3
W9816G6CB 6. block diagram clk cke a10 clock buffer command decoder address buffer refresh counter column counter control signal generator mode register column decoder sense amplifier cell array bank #0 r o w d e c o d e r dq0 dq15 ldqm udqm dq buffer cs ras cas we data control circuit note: the cell array configuration is 2048 * 256 * 16 column decoder sense amplifier cell array bank #1 a0 a9 ba r o w d e c o d e r publ i c at i on rel e ase dat e : aug. 23, 2007 - 6 - revi si on a3
W9816G6CB 7. functional description 7.1 pow e r up and initialization the default power up state of the mode regist er is unspecified. the following power up and initialization sequence need to be followed to guar antee the device being preconditioned to each user specific needs during power up, all v cc and v ccq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "nop" state. the power up voltage must not exceed v cc + 0.3v on any of the input pins or v cc s u p p lie s . afte r p o w e r u p , a n in itia l p a u se of 200 s is required followed by a precharge of all ban ks using the precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all ban ks have been precharged, the mode register set command must be issued to initialize the mode regi ster. an additional eight auto refresh cycles (cbr) are also required before or after progra mming the mode register to ensure proper subsequent operation. 7.2 programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke mu st be high at least one cycle before the mode register set command can be issued. the mode r egister set command is activated by the low signals of ras , ca s , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for m ode register set cycle and operation table. 7.3 bank activate command the bank activate command must be applied befor e any read or write operation can be executed. the operation is similar to ra activate in edo dram. the delay from when the bank activate command is applied to when the first read or writ e operation can begin must not be less than the ras to cas delay time (t s rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is det ermined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank-to-bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max.). 7.4 read and write access modes after a bank has been activated, a read or write cycl e can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the a ccess and precharge operations between multiple banks, seamless data access operation among many di fferent pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle. publ i c at i on rel e ase dat e : aug. 23, 2007 - 7 - revi si on a3
W9816G6CB 7.5 burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of t he clock. the address inputs det ermine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the mode regi ster set up cycle. table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 burst write command the burst write command is initiated by applying logic low level to cs , cas and we while holding ra s high at the rising edge of the clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remain ing data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. 7.7 read interrupted by a read a burst read may be interrupted by another read comm and. when the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. 7.8 read interrupted by a write to interrupt a burst read with a write comm and, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid dat a contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. 7.9 write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 write interrupted by a read a read command will interrupt a burst write operat ion on the same clock cycle that the read command is activated. the dqs must be in the high impedance state at l east one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from t he burst write cycle will be ignored. 7.11 burst stop command a burst stop command may be used to terminate t he existing burst operati on but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other bur st length operations is illegal. the burst stop publ i c at i on rel e ase dat e : aug. 23, 2007 - 8 - revi si on a3
W9816G6CB command is defined by having ra s and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impedance state after a delay, which is equal to the ca s latency in a burst read cycle, interrupted by burs t stop. if a burst stop command is issued during a full page burst write operation, then any residual dat a from the burst write cycle will be ignored. 7.12 addressing sequence of sequential mode a column access is performed by increasing the addre ss from the column address, which is input to the device. the disturb address is varied by the burst length as shown in table 2. table 2 address sequence of sequential mode d a t a a c c e s s a d d r e s s burst l e n g t h data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 7.13 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleav e mode dat a access address burst l e ngt h data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a 8 a7 a6 a5 a4 a3 a2 a1 a0 publ i c at i on rel e ase dat e : aug. 23, 2007 - 9 - revi si on a3
W9816G6CB 7.14 auto-precharge command if a10 is set to high when the read or write comm and is issued, then the auto-precharge function is entered. during auto-precharge, a read command will ex ecute as normal with t he exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain number of clo cks prior to the end of the scheduled burst cycle. the number of clo cks is determined by cas latency. a read or write command with auto-precharge can not be interrupted before the entire burst operation is completed. therefore, use of a r ead, write, or precharge command is prohibited during a read or write cycle with auto-precharge. once the precharge operation has started, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto-precharge command is illegal if the burst is set to full page length. if a 10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enter s the precharge operation two clock delay from the last burst write cy cle. this delay is referred to as write t wr . the bank undergoing auto-precharge can not be reactivated until t wr and t rp are satisfied. this is referred to as t dal , data-in to ac tive delay (t dal = t wr + t rp ). when using the auto-precharge command, the interva l between the bank activate command and the beginni ng of the internal precharge operation must sat i sf y t ras (min). 7.15 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. the address bits, a10, and ba, are used to define which bank(s) is to be precharged when the command is issued. after t he precharge command is issued, the precharged bank must be reactivated before a new read or wr ite access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). 7.16 self refresh command the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self-refresh command. once the command is registered, cke must be held low to keep the device in self-refresh mode. when the sdram has entered self refresh mode all of the external control si gnals, except cke, are disabled. the clock is internally disabled during se lf-refresh operation to save power. the device will exit self-refresh operation after cke is re turned high. any subsequent commands can be issued after t rc from the end of self refresh command. if, during normal operation, auto-refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 auto-r efresh cycles should be completed just prior to entering and just after exiting the self-refresh mode. publ i c at i on rel e ase dat e : aug. 23, 2007 - 10 - revi si on a3
W9816G6CB 7.17 pow e r dow n mode the power down mode is initiated by holding cke low. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations; therefore the device can not remain in powe r down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing c ke high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t cks (min) + t ck (min). 7.18 no operation command the no operation command should be used in cases when the sdram is in an idle or a wait state to prevent the sdram from regist ering any unwanted commands between operations. a no operation command is registered when cs is low with ra s , cas and we held high at the rising edge of the clock. a no operation command will not terminat e a previous operation t hat is still executing, such as a burst read or write cycle. 7.19 deselect command the deselect command performs the same func tion as a no operation command. deselect command occurs when cs is brought high, the ra s , ca s and we signals become don't cares. 7.20 clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clo ck suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends any clo cked operation that was cu rrently being executed. there is a one-clock delay between the registrati on of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bri nging cke high. there is a one-clock cycle delay from when cke returns high to when clock suspend mode is exited. publ i c at i on rel e ase dat e : aug. 23, 2007 - 11 - revi si on a3
W9816G6CB 8. operation mode fully synchronous operations are performed to latc h the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note 1, 2) comma nd device sta t e cken-1 cken d qm ba a 1 0 a 9-a 0 cs ras cas we bank a c t i v e i d l e h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l w r i t e a c t i v e ( 3 ) h x x v l v l h l l write w i th auto-precharge active (3) h x x v h v l h l l r e a d a c t i v e ( 3 ) h x x v l v l h l h read w i th auto-precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no-o p e r a t i o n any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device d e s e l e c t any h x x x x x h x x x a u t o - r e f r e s h i d l e h h x x x x l l l h self-refresh entry idle h l x x x x l l l h sel f -refres h exi t idle (s.r) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry a c t i v e h l x x x x x x x x pow e r dow n mode entry idle ac ti v e (5) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit active l h x x x x x x x x pow e r dow n mode exit any (pow er dow n) l l h h x x x x x x x x h l x h x h x x data write/output enable active h x l x x x x x x x data write/o u tput disable active h x h x x x x x x x notes: (1) v = valid, x = don't care, l = low level, h = high level (2) cken signal is input leve l w hen commands are provided. cken-1 signal is the input level on e clock cy cle before the command is issued. (3) these are state of bank designated by ba signals. (4) device state is full page burst operation. (5) pow e r dow n mode can not be entered in the burst cy cle. when this command asserts in the burst cy cle, device state is clock suspend mode. publ i c at i on rel e ase dat e : aug. 23, 2007 - 12 - revi si on a3
W9816G6CB 9. electrical characteristics 9.1 absolute maximum ratings p a r a m e t e r s y m b o l r a t i n g u n i t n o t e s input, output voltage v in , v out -1 ~ v cc + 0.3 v 1 pow e r supply voltage v cc , v ccq - 1 ~ 4 . 6 v 1 operating t e mperature t opr 0 ~ 70 c 1 storage t e mperature t st g -55 ~ 150 c 1 soldering t e mperature (10s) t sold er 2 6 0 c 1 pow e r dissipation p d 1 w 1 short circuit output current i out 5 0 m a 1 note: ex posure to conditions bey ond those listed under absolute max i mum ratings may adversely affect the life and reliability of the device. 9.2 recommended dc operating conditions (ta = 0 to 70 c) paramet e r s y m . min. t yp. m a x . unit not e s pow e r supply voltage for -6 v cc 3 . 0 3 . 3 3 . 6 v 2 pow e r supply voltage for -7 v cc 2 . 7 3 . 3 3 . 6 v 2 pow e r supply voltage for -6 (for i/o buffer) v ccq 3 . 0 3 . 3 3 . 6 v 2 pow e r supply voltage for -7 (for i/o buffer) v ccq 2 . 7 3 . 3 3 . 6 v 2 input high voltage v ih 2 . 0 - v cc + 0.3 v 2 input low voltage v il - 0 . 3 - 0 . 8 v 2 note : v ih (max.) = v cc /v ccq +1.2v for pulse w i d t h < 5 ns v il (min.) = v ss /v ssq -1.2v for pulse w i d t h < 5 ns 9.3 capacitance (v cc = 3.3v, ta = 25 c, f = 1mhz) paramet e r s y m . m i n . m a x . unit input capacitance (a0 to a10, ba, cs , ra s , ca s , we , udqm, ldqm, cke) c i - 4 p f input capacitance (clk) - 4 pf input/output capacitance (dq0 to dq15) c io - 5 . 5 p f note: these parameters are periodically sampled and not 100% tested publ i c at i on rel e ase dat e : aug. 23, 2007 - 13 - revi si on a3
W9816G6CB 9.4 dc characteristics (v cc = 3.3v 0.3v for -6, v cc = 2.7v to 3.6v for -7, ta = 0 to 70 c) paramet e r s y m . -6 max. -7 max. u n i t n o t e s operating current t ck = min., t rc = min . active precharge command cy cling w i thout burst operation 1 bank operation i cc1 6 0 5 0 3 cke = v ih i cc2 3 0 2 5 3 standby current t ck = min., cs = v ih v i h /l = v ih (min.) /v il (max . ) bank: inactive state cke = v il (pow er dow n mode) i cc2 p 2 2 3 cke = v ih i cc2 s 1 0 1 0 standby current clk = v il , cs = v ih v ih/l = v ih (min.) /v il (max . ) bank: inactive state cke = v il (pow er dow n mode) i cc2 p s 2 2 m a cke = v ih i cc3 4 0 3 5 no operating current t ck = min., cs = v ih (min.) bank: active state (2 banks) cke = v il (pow er dow n mode) i cc3 p 1 0 1 0 burst operating current (t ck = min.) read/ w r ite command cy cling i cc4 1 1 0 1 0 0 3 , 4 auto refresh current (t ck = min.) auto refresh command cy cling i cc5 5 5 5 0 3 self refresh current (cke = 0.2v) self refresh mode i cc6 2 2 m a p a r a m e t e r s y m . min. m a x . u n i t notes input leakage current (0v v in v cc , all other pins not under test = 0v) i i( l) - 5 5 a output leakage current (output disable , 0v v out v ccq ) i o( l) - 5 5 a lvt t l outputt h level voltage (i out = -2 ma) v oh 2 . 4 - v lvt t l output l level voltage (i out = 2 ma) v ol - 0 . 4 v publ i c at i on rel e ase dat e : aug. 23, 2007 - 14 - revi si on a3
W9816G6CB 9.5 ac characteristics (v cc = 3.3v 0.3v for -6, v cc = 2.7v to 3.6v for -7, ta = 0 to 70 c, notes: 5, 6, 7, 8) - 6 - 7 paramet e r s y m . m i n . m a x. m i n . m a x . u n i t n o t e s ref/active to ref/active command period t rc 6 0 6 5 n s active to precharge command period t ra s 4 2 1 0 0 0 0 0 4 5 1 0 0 0 0 0 active to read/w r ite command delay t i me t rcd 1 8 2 0 read/w r ite(a) to read/ w r ite(b)command period t ccd 1 1 t ck precharge to active(b) command period t rp 1 8 1 8 n s active(a) to active(b) command period t rrd 1 2 1 4 cl* = 2 t wr 2 2 t ck write recovery t i me cl* = 3 2 2 cl* = 2 t ck 8 1000 1 0 1 0 0 0 n s clk cy cle t i me cl* = 3 6 1000 7 1000 clk high level w i dth t ch 2 2 9 clk low level w i dth t cl 2 2 9 cl* = 2 t ac 5 . 5 5 . 5 1 0 access t i me from clk c l * = 3 5 5 1 0 output data hold t i me t oh 2 2 . 5 1 0 output data high impedance t i me t hz 2 7 2 . 5 7 8 output data low impedance t i me t lz 0 0 1 0 pow e r dow n mode entry t i me t sb 0 7 0 7 t r ansition t i me of clk (rise and f a ll) t t 0 . 5 1 0 . 5 1 7 data-in-set-up t i me t ds 1 . 5 1 . 5 9 data-in hold t i me t dh 0 . 7 1 9 address set-up t i me t as 1 . 5 1 . 5 9 address hold t i me t ah 0 . 7 1 9 cke set-up t i me t ck s 1 . 5 1 . 5 9 cke hold t i me t ck h 0 . 7 1 9 command set-up t i me t cms 1 . 5 1 . 5 9 command hold t i me t cmh 0 . 7 1 9 refresh t i me t re f 6 4 6 4 m s mode register set cy cle t i me t rs c 1 2 1 4 n s exit self refresh to act i ve command t xs r 7 2 7 5 n s publ i c at i on rel e ase dat e : aug. 23, 2007 - 15 - revi si on a3
W9816G6CB notes: 1. 2. 3. 4. 5. 6. operation exceeds " absolute maximum ratings " may c ause permanent damage to the devices. all voltages are referenced to v ss . ? 2.7v~3.6v power supply for -7 speed grade. ? 3.3v 0.3v power supply for -6 speed grades. these parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . these parameters depend on the output loading c onditions. specified values are obtained with output open. power up sequence please refer to "functi onal description" section described before. ac test condition. p a r a m e t e r c o n d i t i o n s output reference level 1.4v output load see diagram below input signal levels 2.4v/0.4v transition time (t t : tr/tf) of input signal 1/1 ns input reference level 1.4v 50 oh m s 1. 4 v ac t e s t l o a d z = 50 oh m s ou t p u t 30 pf 7. 8 . 9. 10. transition times are measured between v ih and v il . t hz defines the time at which the outputs achiev e the open circuit condition and is not referenced to output level. assumed input rise and fall time (t t ) = 1ns. if tr & tf is longer than 1ns, transient ti me compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter ( t he t t max i mum can?t be more than 10ns for low frequency application. ) i f clock rising t i me (t t ) is longer than 1ns, (t t /2-0.5)ns should be added to the parameter. publ i c at i on rel e ase dat e : aug. 23, 2007 - 16 - revi si on a3
W9816G6CB 10. timing waveforms 10.1 command input timing t c k clk a0 -a1 0 ba v ih v il t cm h t cm s t ch t cl t t t t t ck s t ck h t ck h t ck s t cks t ck h cs ra s cas we ck e t cm s t cm h t cm s t cm h t cm s t cmh t cm s t cmh t as t ah publ i c at i on rel e ase dat e : aug. 23, 2007 - 17 - revi si on a3
W9816G6CB 10.2 read timing r e ad cas l a ten c y t ac t lz t ac t oh t hz t oh bur s t length re ad comm and clk cs ras cas we a0- a 10 ba dq val i d da t a - o u t v a lid data - o ut publ i c at i on rel e ase dat e : aug. 23, 2007 - 18 - revi si on a3
W9816G6CB 10.3 control timing of input/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz open t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0 -15 (word mask) (clock mask) clk cke dq0 -15 clk control timing of input data control timing of output data (output enable) (clock mask) dqm dq0 -15 cke clk dq0 -15 publ i c at i on rel e ase dat e : aug. 23, 2007 - 19 - revi si on a3
W9816G6CB 10.4 mode register set cy cle a0 a3 a0 addre ssing mode a0 0 a0 s equential a0 1 a0 int e rl eave a0 a9 s i ngle write mode a0 0 a0 burs t read and b u rs t write a0 1 a0 burst read and single w r ite a0 a0 a2 a 1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 a0 b u rst leng th a0 s equential a0 interleave 1 a0 1 a0 2 a0 2 a0 4 a0 4 a0 8 a0 8 a0 res e rved a0 res e rved a0 full page a0 ca s latenc y a0 res e rved a0 res e rved 2 a0 3 res e rved a0 a6 a 5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 t rs c t cm s t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah cl k cs ra s cas we a0-a 10 ba r egi st er se t data nex t c o mmand a0 a1 a2 a3 a4 a5 a6 b u rst leng th addre ssing mode ca s latenc y (test mode ) a8 res e rved a0 a7 a0 a9 a0 write mode a1 0 a0 ba "0" "0" "0" reserv ed "0 " publ i c at i on rel e ase dat e : aug. 23, 2007 - 20 - revi si on a3
W9816G6CB 11. operating timing example 11.1 interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 ba we cas ras cs t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 bank #0 bank #1 publ i c at i on rel e ase dat e : aug. 23, 2007 - 21 - revi si on a3
W9816G6CB 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk cke dqm a0-a9 a10 ba we cas ras cs t rc t rc t rc t ras t rp t ras t rp t ras t rp t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing bank #0 bank #1 ap* ap* ap* raa caw rbb cbx rac cay rbd rae cbz rbb publ i c at i on rel e ase dat e : aug. 23, 2007 - 22 - revi si on a3
W9816G6CB 11.3 interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs ba active read precharge active read precharge active t ac t ac read precharge t ac bank #0 bank #1 publ i c at i on rel e ase dat e : aug. 23, 2007 - 23 - revi si on a3
W9816G6CB 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t rc t ras t rp t ras t ras t rp t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby (clk = 100 mhz) rac rac caz * ap is the internal precharge start timing active read active active read t cac t cac t cac clk dq cke dqm a0-a9 a10 ba we cas ras cs bank #0 bank #1 read ap* ap* publ i c at i on rel e ase dat e : aug. 23, 2007 - 24 - revi si on a3
W9816G6CB 11.5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rp t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 (clk = 100 mhz) write precharge active active write precharge active write clk dq cke dqm a0-a9 a10 we cas ras cs ba bank #0 bank #1 t ras publ i c at i on rel e ase dat e : aug. 23, 2007 - 25 - revi si on a3
W9816G6CB 11.6 interleaved bank write (burst length = 8, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t ra s t rp t rcd t rcd t rcd t rrd t rr d raa raa cax rbb rbb cby rab rac ax 0 a x 1 ax 4 ax 5 a x 6 ax 7 b y0 b y 1 by 2 by 3 b y 4 by 5 by 6 b y7 cz0 c z1 cz 2 caz (clk = 100 m h z) * ap i s t h e i n t e r nal pr echar g e st ar t t i m i ng cl k dq ck e dq m a0-a9 a10 we ca s ra s cs ba act i ve wr i t e write act i ve b ank # 0 b ank # 1 ap * act i ve wri t e ap* publ i c at i on rel e ase dat e : aug. 23, 2007 - 26 - revi si on a3
W9816G6CB 11.7 page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t rp t ras t rp t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 (clk = 100 mhz) * ap is the internal precharge start timing clk dq cke dqm a0-a9 a10 we cas ras cs ba active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 bank #1 ap* publ i c at i on rel e ase dat e : aug. 23, 2007 - 27 - revi si on a3
W9816G6CB 11.8 page mode read / write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rp t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 qq q q q q dd d d d (clk = 100 mhz) clk dq cke dqm a0-a9 a10 we cas ras cs ba active read write precharge t ac bank #0 bank #1 publ i c at i on rel e ase dat e : aug. 23, 2007 - 28 - revi si on a3
W9816G6CB 11.9 auto precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq cke dqm a0-a9 a10 ba we cas ras cs t rc t rc t ras t rp t ras t rp t rcd t rcd t ac t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 * ap is the internal precharge start timing bank #0 bank #1 publ i c at i on rel e ase dat e : aug. 23, 2007 - 29 - revi si on a3
W9816G6CB 11.10 auto precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 10 0 mhz ) cl k dq cke dq m a0 -a9 a10 ba we cas ras cs t rc t rc t ras t rp t ra s t rp raa t rcd t rcd ra b rac raa c aw rab c ax rac aw 0 aw 1 a w 2 aw 3 bx0 bx1 bx2 bx 3 acti v e acti v e wr it e ap* active wr it e ap* * a p i s t he i n t e rna l pre c h a rg e st ar t t i mi ng bank #0 bank #1 publ i c at i on rel e ase dat e : aug. 23, 2007 - 30 - revi si on a3
W9816G6CB 11.11 auto refresh cy cle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9 a10 we cas ras cs ba publ i c at i on rel e ase dat e : aug. 23, 2007 - 31 - revi si on a3
W9816G6CB 11.12 self refresh cy cle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 (clk = 100 mhz) clk dq ck e dqm a0 -a 9 a1 0 ba we ca s ra s cs t ck s t sb t ck s t ck s al l bank s pr ech a r g e sel f r e f r es h ent r y a r bi t r a r y cy cl e t rp sel f r e f r es h cyc l e t xs r no ope r at i o n / comma nd i n hi b i t s e lf r e fre s h ex it publ i c at i on rel e ase dat e : aug. 23, 2007 - 32 - revi si on a3
W9816G6CB 11.13 burst read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we ba a10 a0-a9 dqm cke dq (clk = 100 mhz) t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 qq q q d d dq q q q t ac t ac read read single write active bank #0 bank #1 publ i c at i on rel e ase dat e : aug. 23, 2007 - 33 - revi si on a3
W9816G6CB 11.14 pow e r dow n mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 raa ca a r a a cax raa raa ax 0 ax1 ax 2 a x 3 t sb t ck s t ck s t ck s t sb t ck s acti v e st an dby power down mode pr e c harge stand by power do wn mode ac t i ve nop prech a r g e nop ac t i ve note: t he powerdown mod e is en t e red by a sse r t i n g cke "low" . all inpu t / output buff e r s ( e xc ept ck e b u f f ers ) a r e tur n ed off in t h e po wer down mod e . when cke go es high , comman d inp u t mus t be no ope r a tion at n e xt clk r i sing edg e . violating r e f r esh requirements during powe r -down may resu l t i n a loss o f data. cl k dq cke dq m a0- a 9 a10 ba we ca s ra s cs re ad publ i c at i on rel e ase dat e : aug. 23, 2007 - 34 - revi si on a3
W9816G6CB 11.15 auto-precharge timing (read cy cle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq publ i c at i on rel e ase dat e : aug. 23, 2007 - 35 - revi si on a3
W9816G6CB 11.16 auto-precharge timing (write cy cle) act 01 3 2 (1) cas latency = 2 (a) burst length = 1 dq 45 7 68 9 1 1 10 write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 act ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 (2) cas latency = 3 (a) burst length = 1 dq write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 twr twr twr twr twr twr twr twr 12 act represents the write with auto precharge command. represents the start of internal precharing. represents the bank active command. write ap act act when the /auto precharge command is asserted,the period from bank activate command to the start of intermal precgarging must be at least tras (min). note ) clk publ i c at i on rel e ase dat e : aug. 23, 2007 - 36 - revi si on a3
W9816G6CB 11.17 timing chart of read to write cy cle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency=2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency=3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 11.18 timing chart of write to read cy cle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0 publ i c at i on rel e ase dat e : aug. 23, 2007 - 37 - revi si on a3
W9816G6CB 11.19 timing chart of burst stop cy cle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 11.20 timing chart of burst stop cy cle (precharge command) 01 1 1 10 9 8 7 6 5 4 3 2 (1) read cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg read (b) cas latency =3 command q0 q1 q2 q3 q4 prcg read dq dq (2) write cycle (a) cas latency =2 command q0 q1 q2 q3 q4 prcg write (b) cas latency =3 command q0 q1 q2 q3 q4 write dq dq dqm dqm prcg twr twr publ i c at i on rel e ase dat e : aug. 23, 2007 - 38 - revi si on a3
W9816G6CB 11.21 cke/dqm input timing (write cy cle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk publ i c at i on rel e ase dat e : aug. 23, 2007 - 39 - revi si on a3
W9816G6CB 11.22 cke/dqm input timing (read cy cle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk publ i c at i on rel e ase dat e : aug. 23, 2007 - 40 - revi si on a3
W9816G6CB publ i c at i on rel e ase dat e : aug. 23, 2007 - 41 - revi si on a3 12. package specification 12.1 vfbga60ball (6.4x10.10 mm,ball pitch:0.65mm, ? =0.4mm)
W9816G6CB publ i c at i on rel e ase dat e : aug. 23, 2007 - 42 - revi si on a3 13. revision history v e r s i o n d a t e p a g e descript i o n a0 jul. 28, 2003 all preliminary datasheet dec. 18, 2003 15 modified t rp timing parameters dec. 22, 2003 15 modified t wr timing parameters feb. 11, 2004 13 modified power supply voltage range jun. 15, 2005 42 add important notice a1 nov. 10, 2005 3, 14, 15 add -6 speed grade a2 jul. 03, 2006 41 change ball dimension description. a3 aug. 23, 2007 15, 16, 32 1. add t xsr timing specification. 2. add ac characteristics notes 9 and 10 (t t ). 3. revise transient time t t ac test condition in notes 6 of ac characteristics and operating condition. important notice winbond products are not designed, intended, authorized or w a rranted for use as components in sy stems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications w h erein failure of winbond products could result or lead to a situation w h erein personal injury , death or sev ere property or env i ronmental damage could occur. winbond customers using or selling these products for use in such applications do so at their ow n risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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